Novel design of driver and ESD transistors with significantly reduced silicon area

This paper presents three novel design techniques, which combined fulfill all major requirements posed on large driver and Electro Static Discharge (ESD) protection transistors: minimum area consumption, good ESD robustness and optimized normal operation. Transistors protecting 5V/um Human Body Model (HBM) were demonstrated. Significant silicon area reduction was demonstrated in deep-sub micron CMOS, ranging from 0.35um down to 0.13um CMOS. This novel design solution follows standard design flows and does not require any process modifications.